Recently, low power consumption in the field of memory devices has become important especially in the field of dynamic random-access memory (DRAM). A DRAM device or a DRAM chip has several modes of operation including several power saving modes. Besides the active mode in which the DRAM would operate normally, the power saving modes of the DRAM device may include an idle mode, a standby power-down mode, a self refresh mode, and a deep power down mode. The deep power down mode is an extreme power saving mode and does not guarantee data to be safely stored as typically all internal generators operating under the deep power down mode are disabled. For the self refresh mode, data stored in memory cells are guaranteed to be stored safely, but the self refresh mode typically require higher power consumption than other types of power saving modes. In order to guarantee that the data are stored safely, a memory device must consume additional power to perform self refresh operation periodically.
FIG. 1 is a state diagram which shows a conventional memory device entering one of several power saving modes when the memory device is in the idle state. Referring to FIG. 1, in S101, the memory device is assumed to have received a power on instruction. In response to powering on, the memory device would undergo an initialization procedure in a predefined manner and also a reset command would be issued. The initialization procedure would include resetting the memory device to an optimal operating condition as required by the specification of the memory device (S102). In step S103, the memory device would enter the idle mode waiting to be accessed. In step S104, the memory device may enter an active mode so as to perform a typical operation which may include a read/write procedure.
However, once the memory device is in the idle mode S103, the memory device may enter one of three power saving mode which may include a deep power down mode S105, a self refresh mode S106, and a standby power down mode S107. When operating under the deep power down mode S105, all the power generators of the memory device would typically be turned off. When operating under the self refresh mode S106, some or all power generators of the memory device may turn on but powers for functional blocks that are not related to storing data could be switched off or cutoff. Similarly, when operating under the standby power down mode S107, some or all power generators of the memory device may turn on but powers for functional blocks that are not related to storing data could be switched off or cutoff.
Table 1 shows a comparison among various power saving modes as previously described. According to Table 1, the deep power down mode may save the most power relative to other power saving modes but does not guarantee data storage. The standby power down mode achieves worse power saving than the deep power down mode but also does not guarantee data storage. The self refresh mode does guarantee data storage but at the cost of having worse power saving than the deep power down mode.
TABLE 1DeepStandbyModePower DownPower DownSelf RefreshPower SavingBestGoodGoodData MaintainNoNoYesFor further details with regard to the power saving modes, technical specification W978H6KB/W978H2KB is incorporated by reference.
FIG. 2 shows a hardware block diagram of a conventional DRAM device. The DRAM device may include not limited to a memory 201, a control logic circuit 202 electrically connected to a mode register circuit 203, a refresh control & counter 204, a row address multiplexer 205, a bank control logic circuit 206, a column address counter & latch 207, a plurality of row address latch & decoders 208, a plurality of column decoders 209, a I/O gating & DM masking logic circuit 210, a sense amplifier 211, a read/write control logic circuit & Din buffer/Dout Drivers 212, and so forth. Technical specification W978H6KB/W978H2KB may contain further details with regard to the functions of each of the above described blocks.
Essentially, the control logic circuit would receive information from an external command, a memory address, and values stored in the mode registers 203 to at least determine whether to read from or to write data into the memory array 201 as well as whether to enter the active mode S104, the deep power down mode S105, the self refresh mode S106, the standby power-down mode S107, and etc. Such information could be received from a central processor or a controller that is situated external to the memory device 200. The control logic circuit 202 would read from the mode registers 203 to determine whether a read operation or a write operation is to be performed and would also use the receive address (such as which memory bank, sector, page, etc.) to determine where to read or write the data by controlling the row address multiplexer 205, the bank control logic 206, and the row address latch & decoders 208 to determine the bank location (e.g. bank 0, bank 1, bank 2, etc.) and the row address within the determined bank location. Similarly, the control logic circuit 202 would read from the mode registers 203 to determine whether a read operation or a write operation is to be performed and would also use the received address (such as which memory bank, sector, page, etc.) to determine where to read or write the data by controlling the column address counter & latch 207 and the bank control logic 206, and the column decoders 209 to determine the bank location (e.g. bank 0, bank 1, bank 2, etc.) and the column address within the determined bank location.
For the memory device of FIG. 2, there could be several internal power generators and power buses. For example, the power generator and power buses would generate internal voltage (VINT) for periphery circuits (e.g. 202˜212), VINT for the memory array 201, VPP (high voltage) for memory array 201, VBB (negative voltage) for memory array 201, and etc. The internal power generators could all be generated from the same power supply chip and share the same power bus. This could make power saving rather limited.
For example, an application may want to maintain data only in memory bank 0 but does not care for other banks within the memory array 201. Then the conventional self refresh mode may provide self refresh only for memory array bank 0 to maintain the data within bank of the memory array 201 as only bank 0 is intended to consume power during the self refresh operation. However, other banks of the memory array 201 would likely still consume leakage current because internal power generators have connected all memory array banks together. Currently, the leakage current of each individual memory bank is not trivial, and the sum of the leakage current of the entire memory array 201 could be significant. The power consumption due to the leakage current might be even larger than the power consumption of the self refresh current within memory device 200. Similarly, in the periphery circuits (e.g. 202˜212), even though only certain periphery circuits active under the self refresh mode, other periphery circuits not actively supporting the self refresh operation also consume leakage currents because VINT is all connected together. This means that the conventional self refresh mode may not achieve decent power reduction as intended.
In the very near future, it is perceivable that some memory applications not only would require an extreme power saving at a similar level as the deep power down mode but also require at least some of the data stored in a memory device to be guaranteed. Therefore, a mechanism which would be able to achieve extreme power saving but at the same time safely preserve data stored in a memory device would be required.